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120 ma switched capacit or voltage inverter with regulated output data sheet adp3605 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 1998 C 2012 analog devices, in c. all rights reserved. technical support www.analog.com features fully regulated adjustable output voltage high output current : 120 ma output a ccuracy: 3% 250 khz switching frequency low shutdown current : 2 a t ypical input voltage r ange : 3 v to 6 v 8- lead soic p ackage ? 40 c to +85 c ambient temperature range applications voltage i nverters voltage r egulators computer peripherals and add - on cards portable i nstruments battery powered devices pagers and radio control receivers disk d rives mobile p hones functional block dia gram figure 1. general description the adp3605 is a 120 ma regulated output , switched capacitor voltage inverter. it provides a regulated output voltage with minimum voltage loss and requires a minimum number of ext ernal components. in addition, the adp3605 does not require the use of an inductor. pin - for - pin and functionally compatible with the adp3604 , the internal oscillato r of the adp3605 runs at a 500 khz nominal frequency that produces an output switching frequency of 250 khz. this allows for the use of smaller charge pump and filter capacitors. the adp3605 provides an accuracy of 3% with a typical shutdown current of 2 a. it can also operate from a single positive input voltage as low as 3 v. the adp3605 is adjustable via external resistors over a ? 3 v to ? 6 v range. figure 2 . typical application circuit 8 1 2 7 c p + s p d s1 s3 b s2 s4 s n d d n s d n s osc clock gen v in v out v sense sd gnd adp3605 c p ? 3 4 5 feedback contro l loo p 11 135-001 8 7 1 3 4 5 2 + + + ?3.0v v in v sense v in v out *c in 4.7f *c o 4.7f *c p 4.7f c p + gnd adp3605 c p ? sd r1 19k? off *for best performance, 10f is recommended c p : sprague, 293d475x0010b2w c in , c o : t okin, 1e475zy5uc205f on 0 11 135-002
adp3605 data sheet rev. b | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision histo ry ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ........................................................................ 8 applications information ................................................................ 9 capacitor selection .......................................................................9 input capacitor ..............................................................................9 output capacitor ..........................................................................9 pump capacitor .......................................................................... 10 shutdown mode ......................................................................... 10 power dissipation ...................................................................... 10 general board layout guidelines ............................................ 10 adp3605 regulated adjustable output voltage ................... 10 regulated dual supply system ................................................. 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 12/ 12 rev. a to rev. b updated format .................................................................. universal deleted 14 - lead tssop .................................................... universal changes to features section, general descri ption section, and figure 2 .............................................................................................. 1 changes to table summary text prior to table 1 and table 1 ... 3 changes to table 2 ............................................................................ 4 deleted other members of adp36xx family table i; renumbered sequentially ................................................................ 4 deleted figure 4 ; renumbered sequentially ................................. 4 deleted improved load regulation section ................................. 6 deleted maximum output voltage section and figure 15 ......... 7 changes to figure 10 capt ion ......................................................... 7 changes to power dissipation section , regulated adjustable output voltage section , and figure 17 ........................................ 10 updated outline dimensions ................................ ....................... 12 changes to ordering guide .......................................................... 12 7/ 99 rev. 0 to rev. a
data sheet adp3605 rev. b | page 3 of 12 specifications v in = 5.0 v at t a = 25 c, c p = c o = 4.7 f, unless otherwise noted. the c in , c o , and c p capacitors in the typical application circuit ( see figure 2 ) are 4.7 f. see figure 2 conditions. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. table 1. parameter symbol test conditions /comments min typ max unit operating supply range v s 3 6 v supply current i s ? 40 c < t a < +85 c 3 6 ma shutdown mode v sd = v in , ? 40 c < t a < +85 c 2 15 a output resistance open loop r o 9 output ripple voltage v ripple c in = c o = 4.7 f, i load = 60 ma 38 mv i load = 120 ma 75 mv switching frequency f s v in = 5 v , ?40c < t a < +85c 212 250 288 khz shutdown logic input high v ih 2.4 v input current i ih 1 a logic input low v il 0.4 v input current i il 1 a
adp3605 data sheet rev. b | page 4 of 12 absolute maximum rat ings t a = 25 c, unless otherwise noted . table 2. parameter rating input voltage ( v in to gnd, gnd to v out ) 7.5 v input voltage ( v in to v out ) 11 v output short - circuit protection 1 sec power dissipation, 8- lead so ic 660 mw ja 1 150 c/w operating temperature range C 40 c to +85 c storage temperature range C 65 c to +150 c lead temperature (soldering , 10 sec) 300 c vapor phase (60 sec) 215 c infrared (15 sec) 220 c 1 ja is specified for the worst - case conditions wit h the device soldered on a circuit board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 3 . alternative capacitor technologies type life high freq uency temp erature size cost aluminum electrolytic capacitor fair fair fair small low multilayer ceramic capacitor long good poor fair 1 high solid tantalum capacitor above average a verage average average average os - con capacitor above average good good good a verage 1 refer to capacitor manufacturer's data sheet for operation below 0 c. table 4 . recommended capacitor manufacturers manufacturer capacitor capacitor type sprague 672d, 673d, 674d, 678d aluminum e lectrolytic sprague 675d, 173d, 199d tantalum nichicon pf and pl aluminum e lectrolytic mallory tdc and tdl tantalum tokin mlcc multilayer c eramic mur ata grm multilayer c eramic
data sheet adp3605 rev. b | page 5 of 12 pin configuration and function descripti ons figure 3. pin configuration table 5. pin function descriptions pin o. mnemonic description 1 c p + positive terminal for the pump capacitor. 2 gnd device ground. 3 c p ? negative terminal for the pump capacitor. 4 sd logic level shutdown pin. apply logic high or connect to v in to shut down the device. in shutdown mode, the charge pump is turned off, and the quiescent current is reduced to 2 a (typical). apply a logic low or connect to ground for normal operation. 5 v sense output voltage sense line. connect a resistor between this pin and v out to set the desired output voltage. 6 nc no connect. do not connect to this pin. 7 v out regulated negative output voltage. connect a low esr, 4.7 f or larger , capacitor between this pin and the device ground . 8 v in positive supply input voltage. connect a low esr bypass capacitor between this pin and the device ground to minimize supply transients. c p + 1 gnd 2 c p ? 3 sd 4 v in 8 v out 7 nc 6 v sense 5 notes 1. nc = no connec t . do not connect t o this pin. adp3605 top view (not to scale) 11 135-003
adp3605 data sheet rev. b | page 6 of 12 typical performance characteristics figure 4. oscillator frequency vs. supply voltage figure 5. supply current vs. temperature figure 6. oscillator frequency vs. temperature figure 7. average input current vs. output current figure 8. output voltage vs. load current , v out = ? 3.0 v figure 9. supply current vs. supply voltage 270 260 250 3.0 3.5 4.5 4.0 5.0 5.5 6.0 11135-004 oscillator frequency (khz) supply voltage (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?40 ?15 35 10 supply current (ma) in normal mode supply current (a) in shutdown mode 60 85 11135-005 temperature (c) shutdown mode (v sd = v in ) normal mode (v sd = 0v) v in = 5v 300 280 260 240 220 200 ?40 ?15 10 35 60 85 11135-006 oscillator frequency (khz) temperature (c) 140 120 100 80 60 40 20 0 10 30 50 70 90 110 130 11135-007 input current (ma) load current (ma) ?2.5 ?2.6 ?2.7 ?2.8 ?2.9 ?3.0 ?3.1 ?3.2 0 40 80 120 160 200 280 11135-008 output voltage (v) load current (ma) 240 v in = 3v v in = 5v v in = 4.75v v in = 3.5v v in = 6v 3.5 3.0 2.5 1.5 2.0 1.0 0.5 0 7 6 5 4 3 2 1 0 3 4 5 supply current (ma) in normal mode supply current (a) in shutdown mode 6 11135-009 supply voltage (v) shutdown mode (v sd = v in ) normal mode (v sd = 0v)
data sheet adp3605 rev. b | page 7 of 12 figure 10 . start- up under full load figure 11 . enable/disable time under full load 11135-010 a1 ?0.70v 2ms 1v 11135-011 a2 3.9v 2ms 1v
adp3605 data sheet rev. b | page 8 of 12 theory of operation the adp3605 uses a switched capacitor principle to generate a negative voltage from a positive input voltage. an onboard oscillat or generates a 2 - phase clock to control a switching network that transfers charge between the storage capacitors. the switches turn on and off at a 250 khz rate, which is generated from an internal 500 khz oscillator. the basic principle behind the voltage inversion scheme is illustrated in figure 12 and figure 13. figure 12 . adp3605 switch configuration charging the pump capacitor during phase one, s1 and s2 are on , charging the pump capacitor to the input voltage. before the next phase begins, s1 and s2 are turned off as well as s3 and s4 to prevent any overlap. s3 and s4 are turned on during the second phase (see figure 13 ), and the charge stored in the pump capacitor is transferred to the output capacitor. figure 13 . adp3605 switch configuration charging the output capacitor during the second phase, the positive terminal of the pump capacitor is connected to ground through the variable resistance s witch ( s3 ) , and the negative terminal is connected to the output , resulting in a voltage inversion at the output terminal. figure 1 shows t he adp3605 block diagr am . + v in v out c p c o s1 s2 s3 s4 11 135-012 + v in v out c p c o s1 s2 s3 s4 11 135-013
data sheet adp3605 rev. b | page 9 of 12 applications information capacitor selection the high internal oscillator frequency of the adp3605 permits the use of small capacitors for both the pump and the output capacitors. for a given load current, factors affecting the output voltage performance are the following: ? pump (c p ) and output (c o ) capacitance ? esr of the c p and c o when selecting the capacitors, keep in mind that not all manufactur ers guarantee capacitor esr in the range required by the circuit. in general, the esr of the capacitor is inversely proportional to its physical size ; therefore, larger capacitance values and higher voltage ratings tend to reduce esr. becaus e the esr is al so a function of the operating frequency, when selecting a capacitor, en sure that its value is rated at the operating frequency of the circuit . temperature is another factor affecting capacitor performance. figure 14 illustrates the temperature effect on various capacitors . if the circuit has to operate at temperatures significantly different from 25 c, the capacitance and the esr values must be carefully selected to adequately compensate for the change. various capacitor technologies offer improved performance over temperature; for example, certain tanta lum capacitors provide good low temperature esr; however, at a higher cost. table 3 provides the ratings for different types of capacitor technologies to help the designer select the right capacitors for the application . the exact values of c in and c o are not critical. however, low esr capacitors , such as solid tantalum and multilayer ceramic capacitors , are recommended to minimize voltage loss at high currents. table 4 shows a par tial list of the recommended low esr capacitor manufacturers. figure 14 . esr vs. temperature input capacitor a small 1 f input bypass capacitor, preferably with low esr, such as tantalum or multilayer ceramic, is recommended to reduce noise and supply transients and to supply part of the peak input current drawn by the adp3605 . a large capacitor is recommended if the input supply is connected to the adp3605 through long leads, or if the pulse current drawn by the device m ay affect other circuitry through supply coupling. output capac itor the output capacitor (c o ) is alternately charged to the c p voltage when c p is switched in parallel with c o . the esr of c o introduces steps in the v out waveform whenever the charge pump charges c o , which contributes to v out ripple. thus, ceramic or tan talum capacitors are recommended for c o to minimize ripple on the output. figure 15 illustrates the output ripple voltage effect for various capacitance and esr values. note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the esr, no significant reduction in v out ripple is achieved by added capacitance. becaus e output current is supplied solely by the output capacitor, c o , during one - half of the charge pump cycle, peak - to - peak output ripple voltage is calcu lated by o rc l os l ripple esi cf i v + = 2 2 where: i l = load current f s = 250 khz nominal switching frequency c o = 10 f with an esr of 0.15 mv6015.0ma1202 f10 khz 2502 ma012 =+ = ripple v multiple smaller capacitors can be connected in parallel to yield lower esr and lower cost. for lighter loads, proportionally smaller capacitors are required. to reduce high frequency noise, bypass the output with a 0.1 f ceramic capacitor in parallel with the output capacitor. figure 15 . output ripple voltage vs. capacita nce and esr 10 1 0.1 0.01 ?50 0 50 100 11135-014 (65? temperature (c) aluminum ceramic tantalum organic semic 100 80 60 40 20 0 0 20 40 60 80 100 p? p? p? 120 140 160 11135-015 output ripple (mv) capacitance (f) adp3605 ?3.0v output
adp3605 data sheet rev. b | page 10 of 12 pump capacitor the adp3605 alternately charges c p to the input voltage when c p is switched in parallel with the input supply, and then transfers charge to c o when c p is switched in parallel with c o . during the time c p is charging, the peak current is approximately two times the output current. during the time c p is delivering charge to c o , the supply current drops down to about 3 ma. a low esr capacitor has a much greater impact on performance f or c p than c o because current through c p is twice the c o current . therefore, the voltage drop due to c p is about four times the esr of c p times the load current. while the esr of c o affects the output ripple voltage, the voltage drop generated by the esr of c p , combined with the voltage drop due to the output source resistance, determines the maximum available v out . shutdown mode the output of the adp3605 can be disabled by pulling the sd pin (pin 4) high to a ttl/cm os logic compatible level that stop s the internal oscillator. in shutdown mode, the quiescent c urrent is reduced to 2 a (typical). applying a digital low level or tying the sd p in to ground turn s on the output. if the shutdown feature is not used, pin 4 must be tied to the ground pin. power dissipation the power dissipation of the adp3605 circuit must be limited such that the junction temperature of the device does not exceed the maximum junction temperature ra ting. total power dissipation is calculated as p = ( v in ? | v out |) i out + ( v in ) i s w here : i out and i s are output current and supply current , respectively . v in and v out are input and output voltages , respectively. for example , assuming worst - case conditions, v in = 6 v, v out = ? 2.9 v, i out = 120 ma , and i s = 5 ma. calculated device power dissipation is p (6 v ? |? 2.9 v|) 0.12 + (6 v) 0.005 a = 402 mw this is far below the 660 mw power dissipation capability of the adp3605 . general board layout guidelines because the internal switches of the adp3605 turn on and off very fast, good printed circuit board (pcb) layout practices are critical to ensure optimal operation of the device. improper layouts results in poor load regulation, especially under heavy loads. output performance can be improved by f ollowing these simple layout guidelines : ? use adequate gr ound and power traces or pla nes ? use single point ground for device ground and inp ut and output capacitor grounds ? keep external components as close to the device as possible ? use short traces from the input and output capacitors to the input and output pins , respectively adp3605 regulated adjustable output voltage t he regulated output voltage is programmed by a resistor that is inserted between the v sense and v out pins, as illustrated in figure 16 . the inherent limit of the output voltage of a single inverting charge pump stage is ? 1 times the input voltage. the inverse ( that is, negative) scaling factor of 1.00 is reduced somewhat due to losses that increase with output current. to increase the scaling factor to attain a more negative output voltage , an external pump stage can be added with passive components , as is shown in figure 17 . th is s ingle stage increases the inverse scaling factor to a limit of two, although the diode drops limit s the ability to attain that exact 2.00 scaling factor noticeably. even further increases can be achieved with a dditional external pump stages. figure 16 . adjustable regulated output voltage figure 17 . regulated ?7 v from a 5 v input high accuracy on the adjustable output voltage is achieved with the use of precision trimmed internal resistors, which eliminate the need to trim the external resistor or add a second resistor to form a divider. the adjustable output voltage is set by r v out k5.9 5.1 = where v out is in volts and r is in k . ?5 ?4 ?3 0 20 60 40 80 100 5 n? 5 n? 120 11135-016 v out (v) load current (ma) 1 3 4 2 5 8 7 adp3605 v in = 5.0v r v out 8 1 7 5 3 4 2 v in = 5v c in 4.7f c o 4.7f c1 4.7f 10f d2 1n5817 d1 1n5817 c p 4.7f sd gnd adp3605 r1 n? c p + v in v out v sense c p ? + + + + + 11 135-017
data sheet adp3605 rev. b | page 11 of 12 regulated dual supply system the circuit in figure 18 provides regulated positive and negative voltages for systems that require dual supplies from a single battery or power supply. figure 18 . dual supply system 8 4 2 10f c o1 10f 1n5817 c p1 10f sd gnd adp3605 r1 16.5k? 1% c p + v in v out v sense c p ? 5 4 2 sd gnd adp3607-5 c p + v in v out v sense c p ? + c p2 10f c o2 10f + + 2 1 3 1 3 8 v in = +3.3v +5v ?2.6v 7 5 11 135-018
adp3605 data sheet rev. b | page 12 of 12 outline dimensions figure 19 . 8- leadstandard sm all outline package [soic_n] (r- 8) dime nsions shown in millimeters and (inches) ordering guide model 1 output voltage temperature range package description pack age option adp3605ar z adjustable ?40 c to +85 c 8- lead standard small outline package [soic_n], tube r-8 adp3605ar z- r7 a djustable ?40 c to +85 c 8- lead standard small outline package [soic_n], 7 tape and reel r-8 1 z = rohs compliant part. controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 ? 1998 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11135 -0- 12 / 12(b)

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